1. Field of the Invention
The present invention generally relates to a method of fabricating a semiconductor device and, more specifically, to a method of fabricating flat-cell mask read-only memory (ROM) devices.
2. Background of the Invention
Mask read-only memories (MROMs) are categorized as either NAND-type ROMs or NOR-type ROMs. Operating speed of the NAND-type ROMs is low, while operating speed of the NOR-type ROMs high. Cell areas of the NAND-type ROMs are small, while cell areas of the NOR-type ROMs are large. Thus, NAND-type ROMs are advantageous in achieving a high integration level but the NOR-type ROMs are not. A flat NOR-type ROM has been proposed, which has both the advantages of the NAND-type ROMs and the NOR-type ROMs (i.e., high operating speed and small cell area). The flat NOR-type ROM is a kind of mask ROM that does not have a isolating layer or a contact in a unit cell and uses a buried impurity region formed in the semiconductor substrate as a bit line.
FIGS. 1 through 3 are cross-sectional views showing steps for fabricating a flat NOR-type ROM semiconductor device in accordance with the prior art.
Referring to FIG. 1, a buffer oxide layer 20, an anti-reflecting layer 30, and a photoresist layer (not shown) are sequentially formed on a substrate 10. Using conventional photolithographic processes, the photoresist layer is patterned to form photoresist patterns 40 exposing top surfaces of the anti-reflecting layer 30 at predetermined regions. In this case, the anti-reflecting layer 30 is a material layer for the convenience of the photolithographic process that forms the photoresist patterns 40. Generally, the anti-reflecting layer 30 is made of a silicon oxynitride (SiON).
Using the photoresist patterns 40 as ion implantation masks, an ion implantation process is performed to form impurity regions 50 on the semiconductor substrate 10. The ion implantation process implants arsenic (As) ions into the semiconductor substrate 10 through the anti-reflecting layer 30 and the buffer oxide layer 20. In this case, silicon atoms of the semiconductor substrate 10 depart from the lattice structure because of the kinetic energy of the arsenic ions. Thus, lattice defects are found in the impurity regions 50.
Referring to FIG. 2, after forming the impurity regions 50, the photoresist patterns 40 are removed to expose the anti-reflecting layer 30. Afterward, using etchant containing phosphoric acid (H3PO4), the exposed anti-reflecting layer 30 is removed.
Etching the anti-reflecting layer 30 with phosphoric acid harms the buffer oxide layer 20 lying underneath, causing etching damages. Specifically, the thickness variation of the buffer oxide layer 20 increases, causing its physical/electrical properties to degrade. Thus, the buffer oxide layer 20 may not be used as a gate insulating layer of the transistor and is usually eliminated by etchant containing fluoric acid. As a result, an entire top surface of the semiconductor substrate 10 is exposed.
Referring to FIG. 3, gate insulating layers 60 and 65 are formed on the entire surface of the semiconductor substrate after the buffer oxide layer 20 is removed. The gate insulating layers 60 and 65 are important material layers for defining characteristics of a MOS transistor and are preferably formed by a thermal process in order to achieve good operating characteristics.
The thermal process is normally performed at a temperature of about 850° C. The high temperature thermal process causes the impurities in the impurity regions 50 to diffuse. Therefore, buried impurity regions 55 are formed that are wider and deeper than the former impurity regions 50. Each of the buried impurity regions 55 acts as a source/drain of a flat NOR-type ROM and an interconnection for connecting the same.
Meanwhile, to achieve stable properties of a MOS transistor, the gate insulating layers 60 and 65 must be formed to a predetermined thickness (tOX) or more. As shown in FIG. 2, the buffer oxide layer 20 is removed when the anti-reflecting layer 30 is removed, fully exposing the top surface of the semiconductor substrate 10. Thus, the processing time increases and the impurities (i.e., As) in the impurity regions 50 are more widely diffused. At this stage additional processing time is needed to perform thermal processes for forming the gate insulating layer 60 to a thickness of tOX. Moreover, when the top surfaces of the impurity regions 50 are exposed, impurities therein are actively diffused in a horizontal direction. The prior art suffers from a short channel effect as a distance l1 between the buried impurity regions 55 becomes close. The short channel effect is a serious factor that prevents the high integration of semiconductor devices.
In the thermal process, the impurity regions 50 with lattice defects react to oxygen more actively than the impurity regions without lattice defects. Therefore, gate insulating layers 65 of the impurity regions 50 are thicker than gate insulating layers 60 of regions without implanted impurities.
In addition, a gate electrode 70 is formed on the semiconductor substrate 10 including the gate insulating layers 60 and 65. The gate electrodes 70 are preferably formed to cross over the buried impurity regions 55.